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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5 Monolithic 1.5A, 1.25MHz Step-Down Switching Regulators
FEATURES
s s s s s s s s s s s s s
DESCRIPTIO
1.5A Switch in a Small MSOP Package Constant 1.25MHz Switching Frequency High Power Exposed Pad (MS8E) Package Wide Operating Voltage Range: 3V to 25V High Efficiency 0.22 Switch 1.2V Feedback Reference Voltage Fixed Output Voltages of 1.8V, 2.5V, 3.3V, 5V 2% Overall Output Tolerance Uses Low Profile Surface Mount Components Low Shutdown Current: 6A Synchronizable to 2MHz Current Mode Loop Control Constant Maximum Switch Current Rating at All Duty Cycles*
The LT(R)1767 is a 1.25MHz monolithic buck switching regulator. A high efficiency 1.5A, 0.22 switch is included on the die together with all the control circuitry required to complete a high frequency, current mode switching regulator. Current mode control provides fast transient response and excellent loop stability. New design techniques achieve high efficiency at high switching frequencies over a wide operating range. A low dropout internal regulator maintains consistent performance over a wide range of inputs from 24V systems to LiIon batteries. An operating supply current of 1mA improves efficiency, especially at lower output currents. Shutdown reduces quiescent current to 6A. Maximum switch current remains constant at all duty cycles. Synchronization allows an external logic level signal to increase the internal oscillator from 1.4MHz to 2MHz. The LT1767 is available in an 8-pin MSOP fused leadframe package and a low thermal resistance exposed pad package. Full cycle-by-cycle short-circuit protection and thermal shutdown are provided. High frequency operation allows the reduction of input and output filtering components and permits the use of chip inductors.
, LTC and LT are registered trademarks of Linear Technology Corporation. *Patent Pending
APPLICATIO S
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DSL Modems Portable Computers Wall Adapters Battery-Powered Systems Distributed Power
TYPICAL APPLICATIO
12V to 3.3V Step-Down Converter
D2 CMDSH-3 C2 0.1F VIN 12V BOOST VIN OPEN OR HIGH = ON LT1767-3.3 SHDN SYNC FB GND VC CC 1.5nF RC 4.7k *MAXIMUM OUTPUT CURRENT IS SUBJECT TO THERMAL DERATING.
1767 TA01
L1 5H
EFFICIENCY (%)
C3 2.2F CERAMIC
VSW
OUTPUT 3.3V 1.2A*
D1 UPS120
C1 10F CERAMIC
U
Efficiency vs Load Current
95 VIN = 10V VOUT = 5V 90 85 VIN = 5V VOUT = 3.3V 80 75 70 0 0.2 0.4 0.6 0.8 1 LOAD CURRENT (A) 1.2 1.4
1767 TA01a
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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
ABSOLUTE MAXIMUM RATINGS
Input Voltage .......................................................... 25V BOOST Pin Above SW ............................................ 20V Max BOOST Pin Voltage .......................................... 35V SHDN Pin ............................................................... 25V FB Pin Voltage .......................................................... 6V FB Pin Current ....................................................... 1mA
PACKAGE/ORDER INFORMATION
ORDER PART NUMBER
TOP VIEW BOOST VIN SW GND 1 2 3 4 8 7 6 5 SYNC VC FB SHDN
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 110C/W GROUND PIN CONNECTED TO LARGE COPPER AREA
LT1767EMS8 LT1767EMS8-1.8 LT1767EMS8-2.5 LT1767EMS8-3.3 LT1767EMS8-5 MS8 PART MARKING LTLS LTWG LTWD LTWE LTWF
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER Maximum Switch Current Limit Oscillator Frequency Switch On Voltage Drop VIN Undervoltage Lockout VIN Supply Current Shutdown Supply Current Feedback Voltage CONDITION TA = 0C to 125C TA = < 0C 3.3V < VIN < 25V
q
ISW = -1.5A, 0C TA 125C and -1.3A, TA < 0C
q
(Note 3) VFB = VNOM + 17% VSHDN = 0V, VIN = 25V, VSW = 0V
3V < VIN < 25V, 0.4V < VC < 0.9V (Note 3)
FB Input Current
LT1767 (Adj)
2
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WW
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(Note 1)
SYNC Pin Current .................................................. 1mA Operating Junction Temperature Range (Note 2) LT1767E .......................................... - 40C to 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER
TOP VIEW BOOST VIN SW GND 1 2 3 4 8 7 6 5 SYNC VC FB SHDN
MS8E PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 40C/W EXPOSED GND PAD CONNECTED TO LARGE COPPER AREA ON PCB
LT1767EMS8E LT1767EMS8E-1.8 LT1767EMS8E-2.5 LT1767EMS8E-3.3 LT1767EMS8E-5 MS8E PART MARKING LTZG LTZH LTZJ LTZK LTZL
MIN 1.5 1.3 1.1 1.1
TYP 2 1.25 330
MAX 3 3 1.4 1.5 400 500 2.73 1.3 20 45 1.218 1.224 1.836 2.55 3.366 5.1 - 0.5
UNITS A A MHz MHz mV mV V mA A A V V V V V V A
q q q
2.47
2.6 1 6
LT1767 (Adj)
q
1.182 1.176 1.764 2.45 3.234 4.9
1.2 1.8 2.5 3.3 5 - 0.25
LT1767-1.8 LT1767-2.5 LT1767-3.3 LT1767-5
q q q q q
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ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER FB Input Resistance CONDITION LT1767-1.8 LT1767-2.5 LT1767-3.3 LT1767-5 0.4V < VC < 0.9V IVC = 10A VFB = VNOM - 17% VFB = VNOM + 17% Duty Cycle = 0% VC = 1.2V, ISW = 400mA
q q q q q q q q
MIN 10.5 14.7 19 29 150 500 80 70
TYP 15 21 27.5 42 350 850 120 110 2.5 0.35 0.9
MAX 21 30 39 60 1300 160 180
UNITS k k k k Mho A A A/V V V % %
Error Amp Voltage Gain Error Amp Transconductance VC Pin Source Current VC Pin Sink Current VC Pin to Switch Current Transconductance VC Pin Minimum Switching Threshold VC Pin 1.5A ISW Threshold Maximum Switch Duty Cycle Minimum Boost Voltage Above Switch Boost Current SHDN Threshold Voltage SHDN Input Current (Shutting Down) SHDN Threshold Current Hysteresis SYNC Threshold Voltage SYNC Input Frequency SYNC Pin Resistance
85 80
90 1.8 10 30 2.7 15 45 1.40 -13 10 2.2 2 20
ISW = -1.5A, 0C TA 125C and -1.3A, TA < 0C ISW = - 0.5A (Note 4) ISW = -1.5A, 0C TA 125C and -1.3A, TA < 0C (Note 4) SHDN = 60mV Above Threshold SHDN = 100mV Below Threshold
q q q q q q
V mA mA V A A V MHz k
1.27 -7 4 1.5
1.33 -10 7 1.5
ISYNC = 1mA
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1767E is guaranteed to meet performance specifications from 0C to 125C. Specifications over the - 40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls.
Note 3: Minimum input voltage is defined as the voltage where the internal regulator enters lockout. Actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. See Applications Information. Note 4: Current flows into the BOOST pin only during the on period of the switch cycle.
TYPICAL PERFORMANCE CHARACTERISTICS
FB vs Temperature (Adj)
1.22 400 125C 350
SWITCH VOLTAGE (mV)
1.21
FREQUENCY (MHz)
FB VOLTAGE (V)
1.20
1.19
1.18 -50
-25
0 25 50 75 TEMPERATURE (C)
UW
100
Switch On Voltage Drop
1.50 1.45
25C
Oscillator Frequency
300 250
1.40 1.35 1.30 1.25 1.20 1.15 1.10 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
-40C 200 150 100 50
125
1767 G01
0
0
0.5 1 SWITCH CURRENT (A)
1.5
1767 G02
1767 G03
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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5 TYPICAL PERFOR A CE CHARACTERISTICS
SHDN Threshold vs Temperature
1.40
1.38
SHDN THRESHOLD (V)
VIN CURRENT (A)
SHDN INPUT (A)
1.36
1.34
1.32
1.30 -50
-25
0 25 50 75 TEMPERATURE (C)
Minimum Input Voltage for 2.5V Out
3.5 300
3.3 INPUT VOLTAGE (V) VIN CURRENT (A)
VIN CURRENT (A)
3.1
2.9
2.7
2.5 0.001
0.1 0.01 LOAD CURRENT (A)
Current Limit Foldback
2.0 40 1.5
SWITCH PEAK CURRENT (A)
OUTPUT CURRENT (A)
SWITCH CURRENT 1.0 20
1.1
OUTPUT CURRENT (A)
1.5
0.5 FB CURRENT 0
0
0.2
0.4 0.6 0.8 FEEDBACK VOLTAGE (V)
4
UW
100
1767 G04
SHDN Supply Current vs VIN
7 SHDN = 0V 6 5 4 3 2 1 0 0 5 10 15 VIN (V) 20 25 30
1767 G05
SHDN IP Current vs Temperature
-12 -10 SHUTTING DOWN -8 -6 -4 -2 0 -50
STARTING UP
125
-25
0 25 50 75 TEMPERATURE (C)
100
125
1767 G06
SHDN Supply Current
1200 VIN = 15V 250 200 150 100 50 0 1000 800 600 400 200 0
Input Supply Current
MINIMUM INPUT VOLTAGE
1
1767 G07
0
0.2
0.4 0.6 0.8 1 1.2 SHUTDOWN VOLTAGE (V)
1.4
0
5
10 15 20 INPUT VOLTAGE (V)
25
30
1767 G09
1767 G08
Maximum Load Current, VOUT = 5V
1.5
Maximum Load Current, VOUT = 2.5V
1.3 30 L = 4.7H 1.3
L = 4.7H
FB INPUT CURRENT (A)
L = 2.2H 1.1 L = 1.5H 0.9
0.9
L = 2.2H
10
0.7 L = 1.5H
1
0 1.2
1767 G10
0.5 0 5 10 15 INPUT VOLTAGE (V) 20 25
1767 G11
0.7 0 5 10 15 INPUT VOLTAGE (V) 20 25
1767 G12
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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
PIN FUNCTIONS
FB: The feedback pin is used to set output voltage using an external voltage divider that generates 1.2V at the pin with the desired output voltage. The fixed voltage 1.8V, 2.5V, 3.3V and 5V versions have the divider network included internally and the FB pin is connected directly to the output. If required, the current limit can be reduced during start up or short-circuit when the FB pin is below 0.5V (see the Current Limit Foldback graph in the Typical Performance Characteristics section). An impedance of less than 5k (adjustable part only) at the FB pin is needed for this feature to operate. BOOST: The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.22 FET structure. VIN: This is the collector of the on-chip power NPN switch. This pin powers the internal circuitry and internal regulator. At NPN switch on and off, high dI/dt edges occur on this pin. Keep the external bypass capacitor and catch diode close to this pin. All trace inductance in this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. GND: The GND pin acts as the reference for the regulated output, so load regulation will suffer if the "ground" end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. Keep the path between the input bypass and the GND pin short. The GND pin of the MS8 package is directly attached to the internal tab. This pin should be attached to a large copper area to improve thermal resistance. The exposed pad of the MS8E package is also connected to GND. This should be soldered to a large copper area to improve its thermal resistance. VSW: The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the switch pin negative during switch off time. Negative voltage must be clamped with an external catch diode with a VBR <0.8V. SYNC: The sync pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 20% and 80% duty cycle. The synchronizing range is equal to initial operating frequency, up to 2MHz. See Synchronization section in Applications Information for details. When not in use, this pin should be grounded. SHDN: The shutdown pin is used to turn off the regulator and to reduce input drain current to a few microamperes. The 1.33V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from operating until the input voltage has reached a predetermined level. Float or pull high to put the regulator in the operating mode. VC: The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally used for frequency compensation, but can do double duty as a current clamp or control loop override. This pin sits at about 0.35V for very light loads and 0.9V at maximum load. It can be driven to ground to shut off the output.
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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
BLOCK DIAGRAM
The LT1767 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on. When switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor
0.01 VIN 2
2.5V BIAS REGULATOR
SYNC
8
SHUTDOWN COMPARATOR
1.33V
3A ERROR AMPLIFIER gm = 850Mho
7 VC
Figure 1. Block Diagram
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-
SHDN
5
+
W
and output capacitor, then an abrupt 180 shift will occur. The current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. High switch efficiency is attained by using the BOOST pin to provide a voltage to the switch driver which is higher than the input voltage, allowing switch to be saturated. This boosted voltage is generated with an external capacitor and diode. A comparator connected to the shutdown pin disables the internal regulator, reducing supply current.
+
INTERNAL VCC
-
CURRENT SENSE AMPLIFIER VOLTAGE GAIN = 40
SLOPE COMP
0.35V
1
BOOST
1.25MHz OSCILLATOR
S CURRENT COMPARATOR
RS FLIP-FLOP
DRIVER CIRCUITRY
+ -
7A
R
Q1 POWER SWITCH
3
VSW
-
+
PARASITIC DIODES DO NOT FORWARD BIAS
6
FB
1.2V 4 GND
1767 F01
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
FB RESISTOR NETWORK If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required, the respective fixed option part, -1.8, -2.5, -3.3 or -5, should be used. The FB pin is tied directly to the output; the necessary resistive divider is already included on the part. For other voltage outputs, the adjustable part should be used and an external resistor divider added. The suggested resistor (R2) from FB to ground is 10k. This reduces the contribution of FB input bias current to output voltage to less than 0.25%. The formula for the resistor (R1) from VOUT to FB is: of capacitance is less important and has no significant effect on loop stability. If operation is required close to the minimum input required by the output of the LT1767, a larger value may be required. This is to prevent excessive ripple causing dips below the minimum operating voltage, resulting in erratic operation. If tantalum capacitors are used, values in the 22F to 470F range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series are surge rated. AVX recommends derating capacitor operating voltage by 2:1 for high surge applications. OUTPUT CAPACITOR
OUTPUT
R1 =
R2 VOUT - 1. 2
1.2 - R2(0.25A)
VSW ERROR AMPLIFIER
(
)
LT1767
+ -
1.2V FB R1
+
R2 10k
1767 F02
VC
GND
Figure 2. Feedback Network
INPUT CAPACITOR Step-down regulators draw current from the input supply in pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the voltage ripple this causes at the input of LT1767 and force the switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from:
IRIPPLE(RMS) = IOUT VOUT VIN - VOUT
(
) / VIN2
Higher value, lower cost ceramic capacitors are now available in smaller case sizes. These are ideal for input bypassing since their high frequency capacitive nature removes most ripple current rating and turn-on surge problems. At higher switching frequency, the energy storage requirement of the input capacitor is reduced so values in the range of 1F to 4.7F are suitable for most applications. Y5V or similar type ceramics can be used since the absolute value
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Unlike the input capacitor, RMS ripple current in the output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is triangular, with an RMS value given by: IRIPPLE(RMS) = 0.29 VOUT VIN - VOUT
( )( (L)(f)(VIN)
)
The LT1767 will operate with both ceramic and tantalum output capacitors. Ceramic capacitors are generally chosen for their small size, very low ESR (effective series resistance), and good high frequency operation, reducing output ripple voltage. Their low ESR removes a useful zero in the loop frequency response, common to tantalum capacitors. To compensate for this, the VC loop compensation pole frequency must typically be reduced by a factor of 10. Typical ceramic output capacitors are in the 1F to 10F range. Since the absolute value of capacitance defines the pole frequency of the output stage, an X7R or X5R type ceramic, which have good temperature stability, is recommended. Tantalum capacitors are usually chosen for their bulk capacitance properties, useful in high transient load applications. ESR rather than capacitive value defines output ripple at 1.25MHz. Typical LT1767 applications require a tantalum capacitor with less than 0.3 ESR at 22F to 500F, see Table 2.
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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
Table 2. Surface Mount Solid Tantalum Capacitor ESR and Ripple Current E Case Size ESR (Max, ) Ripple Current (A)
AVX TPS, Sprague 593D AVX TAJ D Case Size AVX TPS, Sprague 593D C Case Size AVX TPS 0.2 (typ) 0.5 (typ) 0.1 to 0.3 0.7 to 1.1 0.1 to 0.3 0.7 to 0.9 0.7 to 1.1 0.4
Figure 3 shows a comparison of output ripple for a ceramic and tantalum capacitor at 200mA ripple current.
VOUT USING 47F, 0.1 TANTALUM CAPACITOR (10mV/DIV)
VOUT USING 2.2F CERAMIC CAPACITOR (10mV/DIV)
VSW (5V/DIV)
0.2s/DIV
Figure 3. Output Ripple Voltage Waveform
INDUCTOR CHOICE AND MAXIMUM OUTPUT CURRENT Maximum output current for a buck converter is equal to the maximum switch rating (IP) minus one half peak to peak inductor current. In past designs, the maximum switch current has been reduced by the introduction of slope compensation. Slope compensation is required at duty cycles above 50% to prevent an affect called subharmonic oscillation (see Application Note 19 for details). The LT1767 has a new circuit technique that maintains a constant switch current rating at all duty cycles. (Patent Pending) For most applications, the output inductor will be in the 1H to 10H range. Lower values are chosen to reduce the physical size of the inductor, higher values allow higher output currents due to reduced peak to peak ripple current,
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and reduces the current at which discontinuous operation occurs. The following formula gives maximum output current for continuous mode operation, implying that the peak to peak ripple (2x the term on the right) is less than the maximum switch current. Continuous Mode IOUT (MAX) = IP -
(VOUT )(VIN - VOUT ) 2(L)( f)(VIN )
Discontinuous operation occurs when
IOUT (DIS) =
(VOUT ) 2(L)(f)
For VIN = 8V, VOUT = 5V and L = 3.3H, IOUT (MAX) = 1.5 -
2 3.3 * 10- 6 1.25 * 106 8
= 1.5 - 0.23 = 1.27 A Note that the worst case (minimum output current available) condition is at the maximum input voltage. For the same circuit at 15V, maximum output current would be only 1.1A.
1767 F03
(
(5)(8 - 5)
)(
)( )
When choosing an inductor, consider maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault current in the inductor, saturation, and of course, cost. The following procedure is suggested as a way of handling these somewhat complicated and conflicting requirements. 1. Choose a value in microhenries from the graphs of maximum load current. Choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the LT1767 is designed to work well in either mode. Assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. If maximum load current is 0.5A, for instance, a 0.5A inductor may not survive a continuous 2A overload condition. Also, the instantaneous application of input or release from shutdown, at high input voltages, may cause
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LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
saturation of the inductor. In these applications, the soft-start circuit shown in Figure 10 should be used. 2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so don't omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. IPEAK = IOUT + VOUT VIN - VOUT 2 L f VIN 4. After making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. Use the experts in the Linear Technology's applications department if you feel uncertain about the final choice. They have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc. CATCH DIODE The suggested catch diode (D1) is a UPS120 Schottky, or its Motorola equivalent, MBRM120LTI/MBRM130LTI. It is rated at 2A average forward current and 20V/30V reverse voltage. Typical forward voltage is 0.5V at 1A. The diode conducts current only during switch off time. Peak reverse voltage is equal to regulator input voltage. Average forward current in normal operation can be calculated from:
ID ( AVG) = IOUT VIN - VOUT VIN
( )( )( )
(
)
VIN = Maximum input voltage f = Switching frequency, 1.25MHz 3. Decide if the design can tolerate an "open" core geometry like a rod or barrel, which have high magnetic field radiation, or whether it needs a closed core like a toroid to prevent EMI problems. This is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem.
Table 3
PART NUMBER Coiltronics TP1-2R2 TP2-2R2 TP3-4R7 TP4- 100 Murata LQH1C1R0M04 LQH3C1R0M24 LQH3C2R2M24 LQH4C1R5M04 Sumida CD73- 100 CDRH4D18-2R2 CDRH5D18-6R2 CDRH5D28-100 10 2.2 6.2 10 1.44 1.32 1.4 1.3 0.080 0.058 0.071 0.048 3.5 1.8 1.8 2.8 1.0 1.0 2.2 1.5 0.51 1.0 0.79 1.0 0.28 0.06 0.1 0.09 1.8 2.0 2.0 2.6 2.2 2.2 4.7 10 1.3 1.5 1.5 1.5 0.188 0.111 0.181 0.146 1.8 2.2 2.2 3.0 VALUE (uH) ISAT(Amps) DCR () HEIGHT (mm)
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BOOST PIN For most applications, the boost components are a 0.1F capacitor and a CMDSH-3 diode. The anode is typically connected to the regulated output voltage to generate a voltage approximately VOUT above VIN to drive the output stage. The output driver requires at least 2.7V of headroom throughout the on period to keep the switch fully saturated. However, the output stage discharges the boost capacitor during the on time. If the output voltage is less than 3.3V, it is recommended that an alternate boost supply is used. The boost diode can be connected to the input, although, care must be taken to prevent the 2x VIN boost voltage from exceeding the BOOST pin absolute maximum rating. The additional voltage across the switch driver also increases power loss, reducing efficiency. If available, an independent supply can be used with a local bypass capacitor. A 0.1F boost capacitor is recommended for most applications. Almost any type of film or ceramic capacitor is
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APPLICATIONS INFORMATION
suitable, but the ESR should be <1 to ensure it can be fully recharged during the off time of the switch. The capacitor value is derived from worst-case conditions of 700ns on-time, 50mA boost current, and 0.7V discharge ripple. This value is then guard banded by 2x for secondary factors such as capacitor tolerance, ESR and temperature effects. The boost capacitor value could be reduced under less demanding conditions, but this will not improve circuit operation or efficiency. Under low input voltage and low load conditions, a higher value capacitor will reduce discharge ripple and improve start up operation. SHUTDOWN AND UNDERVOLTAGE LOCKOUT Figure 4 shows how to add undervoltage lockout (UVLO) to the LT1767. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur.
LT1767 VIN R1 IN 3A 7A 1.33V VCC VSW OUTPUT
SHDN C1 R2 GND
Figure 4. Undervoltage Lockout
An internal comparator will force the part into shutdown below the minimum VIN of 2.6V. This feature can be used to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the shutdown pin can be used. The threshold voltage of the shutdown pin comparator is 1.33V. A 3A internal current source defaults the open pin condition to be operating (see Typical Performance Graphs). Current hysteresis is added above the SHDN threshold. This can be used to set voltage hysteresis of the UVLO using the following:
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R1 = R2 =
VH - VL 7A
(VH - 1.33V) + 3A
R1
1.33V
VH - Turn-on threshold VL - Turn-off threshold Example: switching should not start until the input is above 4.75V and is to stop if the input falls below 3.75V. VH = 4.75V VL = 3.75V R1 = R2 = 4.75V - 3.75V = 143k 7A 1.33V 143k
(4.75V - 1.33V) + 3A
= 49.4k
+
Keep the connections from the resistors to the SHDN pin short and make sure that the interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the SHDN pin should be bypassed with a 1nF capacitor to prevent coupling problems from the switch node. SYNCHRONIZATION
1767 F04
The SYNC pin, is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 20% and 80%. The input can be driven directly from a logic level output. The synchronizing range is equal to initial operating frequency up to 2MHz. This means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (1.5MHz), not the typical operating frequency of 1.25MHz. Caution should be used when synchronizing above 1.6MHz because at higher sync frequencies the amplitude of the internal slope compensation used to
sn1767 1767fas
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. LAYOUT CONSIDERATIONS As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 5, must be kept as short as possible. This is implemented in the suggested layout of Figure 6. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT1767 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT1767 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise.
LT1767 VIN SW L1 5V
VIN C3
HIGH FREQUENCY CIRCULATING PATH
D1 C1
LOAD
Figure 5. High Speed Switching Path
The VC and FB components should be kept as far away as possible from the switch and boost nodes. The LT1767 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation.
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Board layout also has a significant effect on thermal resistance. Soldering the exposed pad to as large a copper area as possible and placing feedthroughs under the pad to a ground plane, will reduce die temperature and increase the power capacity of the LT1767. For the nonexposed package, Pin 4 is connected directly to the pad inside the package. Similar treatment of this pin will result in lower die temperatures. THERMAL CALCULATIONS Power dissipation in the LT1767 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. Switch loss:
PSW = RSW IOUT
VIN Boost current loss for VBOOST = VOUT:
( ) (VOUT ) + 17ns(IOUT )(VIN)(f)
2
PBOOST =
VOUT IOUT / 50 VIN
2
(
)
Quiescent current loss:
PQ = VIN 0.001
(
)
RSW = Switch resistance ( 0.27 when hot) 17ns = Equivalent switch current/voltage overlap time f = Switch frequency Example: with VIN = 10V, VOUT = 5V and IOUT = 1A:
1767 F05
(0.27)(1) (5) + 17 * 10-9 (1)(10) 1.25 * 106 PSW =
2
10 = 0.135 + 0.21 = 0.34 W
2
(
)
(
)
(5) (1/ 50) = 0.05W PBOOST =
10 PQ = 10 0.001 = 0.01W
(
)
sn1767 1767fas
11
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
D2 CMDSH-3 C2 0.1F VIN 12V BOOST VIN OPEN OR HIGH = ON LT1767-2.5 SHDN SYNC FB GND VC CC 1.5nF RC 4.7k
1767 F06a
C3 2.2F CERAMIC
MINIMIZE LT1767, C3, D1 LOOP D2 C2
L1
Figure 6. Typical Application and Suggested Layout (Topside Only Shown)
Total power dissipation is 0.34 + 0.05 + 0.01 = 0.4W. Thermal resistance for LT1767 package is influenced by the presence of internal or backside planes. With a full plane under the package, thermal resistance for the exposed pad package will be about 40C/W. No plane will increase resistance to about 150C/W. To calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: TJ = TA + JA (PTOT)
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VIN
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L1 5H
VSW
OUTPUT 2.5V 1.2A
D1 UPS120
C1 10F CERAMIC
C3 GND PLACE FEEDTHROUGHS AROUND GROUND PIN AND UNDER GROUND PAD FOR GOOD THERMAL CONDUCTIVITY SYNC KEEP FB AND VC COMPONENTS AWAY FROM HIGH INPUT COMPONENTS
SHDN
D1
CC
RC
C1 VOUT
GND
CONNECT TO GROUND PLANE
KELVIN SENSE VOUT
1767 F06
When estimating ambient, remember the nearby catch diode and inductor will also be dissipating power.
PDIODE =
(VF )(VIN - VOUT )(ILOAD )
VIN
VF = Forward voltage of diode (assume 0.5V at 1A)
PDIODE =
(0.5)(12 - 5)(1) = 0.29W
12
sn1767 1767fas
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
Notice that the catch diode's forward voltage contributes a significant loss in the overall system efficiency. A larger, lower VF diode can improve efficiency by several percent. PINDUCTOR = (ILOAD) (LDCR) LDCR = Inductor DC resistance (assume 0.1) PINDUCTOR = (1) (0.1) = 0.1W Typical thermal resistance of the board is 35C/W. At an ambient temperature of 65C, Tj = 65 + 40 (0.4) + 35 (0.39) = 95C If a true die temperature is required, a measurement of the SYNC to GND pin resistance can be used. The SYNC pin resistance across temperature must first be calibrated, with no device power, in an oven. The same measurement can then be used in operation to indicate the die temperature.
GAIN (dB)
GND VC R2 CF 500k LT1767 CURRENT MODE POWER STAGE gm = 2.5mho VSW ERROR AMPLIFIER FB gm = 850mho R1 TANTALUM CERAMIC ESR ESL C1 OUTPUT
RC CC
Figure 7. Model for Loop Response
80 60 40 VOUT = 5V COUT = 100F, 0.1 CC = 330pF RC/CF = N/C ILOAD = 500mA PHASE 180 150 120 90 60 GAIN -20 -40 30 0 1M
1767 F10
FREQUENCY COMPENSATION Before starting on the theoretical analysis of frequency response, the following should be remembered - the worse the board layout, the more difficult the circuit will be to stabilize. This is true of almost all high frequency analog circuits, read the `LAYOUT CONSIDERATIONS' section first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or catch diode, and connecting the VC compensation to a ground track carrying significant switch current. In addition, the theoretical analysis considers only first order non-ideal component behavior. For these reasons, it is important that a final stability check is made with production layout and components. The LT1767 uses current mode control. This alleviates many of the phase shift problems associated with the inductor. The basic regulator loop is shown in Figure 7, with both tantalum and ceramic capacitor equivalent circuits. The LT1767 can be considered as two gm blocks, the error amplifier and the power stage. Figure 8 shows the overall loop response with a 330pF VC capacitor and a typical 100F tantalum output capacitor. The response is set by the following terms:
20 0
10
100
Figure 8. Overall Loop Response
Error amplifier: DC gain set by gm and RL = 850 * 500k = 425. Pole set by CF and RL = (2 * 500k * 330p)-1 = 965Hz. Unity-gain set by CF and gm = (2 * 330p * 850-1)-1 = 410kHz. Power stage: DC gain set by gm and RL (assume 10) = 2.5 * 10 = 25. Pole set by COUT and RL = (2 * 100 * 10)-1 = 159Hz. Unity-gain set by COUT and gm = (2 * 100 * 2.5-1)-1 = 3.98kHz. Tantalum output capacitor: Zero set by COUT and CESR = (2 * 100 * 0.1)-1 = 15.9kHz.
-
+
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1.2V
+
C1
1767 F07
PHASE (DEG)
1k 10k FREQUENCY (Hz)
100k
sn1767 1767fas
13
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
The zero produced by the ESR of the tantalum output capacitor is very useful in maintaining stability. Ceramic output capacitors do not have a zero due to very low ESR, but are dominated by their ESL. They form a notch in the 1MHz to 10MHz range. Without this zero, the VC pole must be made dominant. A typical value of 2.2nF will achieve this. If better transient response is required, a zero can be added to the loop using a resistor (RC) in series with the compensation capacitor. As the value of RC is increased, transient response will generally improve, but two effects limit its value. First, the combination of output capacitor ESR and a large RC may stop loop gain rolling off altogether. Second, if the loop gain is not rolled sufficiently at the switching frequency, output ripple will perturb the VC pin enough to cause unstable duty cycle switching similar to subharmonic oscillation. This may not be apparent at the output. Small signal analysis will not show this since a continuous time system is assumed. If needed, an additional capacitor (CF) can be added to form a pole at typically one fifth the switching frequency (If RC = ~ 5k, CF = ~ 100pF). When checking loop stability, the circuit should be operated over the application's full voltage, current and temperature range. Any transient loads should be applied and the output voltage monitored for a well-damped behavior. See Application Note 76 for more details. CONVERTER WITH BACKUP OUTPUT REGULATOR In systems with a primary and backup supply, for example, a battery powered device with a wall adapter input, the output of the LT1767 can be held up by the backup supply with its input disconnected. In this condition, the SW pin will source current into the VIN pin. If the SHDN pin is held at ground, only the shut down current of 6A will be pulled via the SW pin from the second supply. With the SHDN pin floating, the LT1767 will consume its quiescent operating current of 1mA. The VIN pin will also source current to any other components connected to the input line. If this load is greater than 10mA or the input could be shorted to ground, a series Schottky diode must be added, as shown in Figure 9. With these safeguards, the output can be held at voltages up to the VIN absolute maximum rating. BUCK CONVERTER WITH ADJUSTABLE SOFT-START Large capacitive loads or high input voltages can cause high input currents at start-up. Figure 10 shows a circuit that limits the dv/dt of the output at start-up, controlling the capacitor charge rate. The buck converter is a typical configuration with the addition of R3, R4, CSS and Q1. As the output starts to rise, Q1 turns on, regulating switch current via the VC pin to maintain a constant dv/dt at the output. Output rise time is controlled by the current through CSS defined by R4 and Q1's VBE. Once the output is in regulation, Q1 turns off and the circuit operates normally. R3 is transient protection for the base of Q1.
RiseTime = (R4)(C SS )(VOUT ) (VBE )
14
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Using the values shown in Figure 10,
RiseTime =
(47 * 103 )(15 * 10-9 )(5) = 5ms 0.7
The ramp is linear and rise times in the order of 100ms are possible. Since the circuit is voltage controlled, the ramp rate is unaffected by load characteristics and maximum output current is unchanged. Variants of this circuit can be used for sequencing multiple regulator outputs. Dual Output SEPIC Converter The circuit in Figure 11 generates both positive and negative 5V outputs with a single piece of magnetics. The two inductors shown are actually just two windings on a standard B H Electronics inductor. The topology for the 5V output is a standard buck converter. The - 5V topology would be a simple flyback winding coupled to the buck converter if C4 were not present. C4 creates a SEPIC (single-ended primary inductance converter) topology which improves regulation and reduces ripple current in L1. Without C4, the voltage swing on L1B compared to L1A would vary due to relative loading and coupling losses. C4 provides a low impedance path to maintain an equal voltage swing in L1B, improving regulation. In a flyback converter, during switch on time, all the converter's energy is stored in L1A only, since no current flows in L1B. At switch off, energy is transferred by magnetic coupling into L1B, powering the - 5V rail. C4 pulls L1B positive
sn1767 1767fas
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
during switch on time, causing current to flow, and energy to build in L1B and C4. At switch off, the energy stored in both L1B and C4 supply the -5V rail. This reduces the current in L1A and changes L1B current waveform from square to triangular. For details on this circuit, including maximum output currents, see Design Note 100.
CMDSH-3 0.1F UPS120* REMOVABLE INPUT VIN 83k LT1767-3.3 SHDN SYNC GND 28.5k 2.2F 4.7k
1767 F09
* ONLY REQUIRED IF INPUT CAN SINK >10mA
Figure 9. Dual Source Supply with 6A Reverse Leakage
C2 0.1F
D2 CMDSH-3 C2 0.1F VIN 12V BOOST VIN LT1767-5 SHDN SYNC FB GND VC CC 330pF Q1 D1: UPS120 Q1: 2N3904 CSS R3 15nF 2k
1767 F10
L1 5H
+
C3 2.2F
VSW D1
+ C1
100F
R4 47k
Figure 10. Buck Converter with Adjustable Soft-Start
PACKAGE DESCRIPTION
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.043 (1.10) MAX 0.007 (0.18) 0.021 0.006 (0.53 0.015) 0 - 6 TYP SEATING PLANE 0.193 0.006 (4.90 0.15) 0.118 0.004** (3.00 0.102) 0.034 (0.86) REF 0.118 0.004* (3.00 0.102)
0.009 - 0.015 (0.22 - 0.38)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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BOOST VSW FB VC 1.5nF UPS120
5H 3.3V, 1A ALTERNATE SUPPLY
2.2F
D2 CMDSH-3
VIN 6V TO 15V
BOOST VIN LT1767-5 SHDN SYNC GND C3 2.2F 16V CERAMIC VSW FB VC CC 330pF
L1A* 9H
OUTPUT 5V
OUTPUT 5V 1A
+
D1
C1 100F 10V TANT
GND C4 2.2F * L1 IS A SINGLE CORE WITH TWO WINDINGS 16V BH ELECTRONICS #511-1013 IF LOAD CAN GO TO ZERO, CERAMIC AN OPTIONAL PRELOAD OF 1k TO 5k MAY BE USED TO IMPROVE LOAD REGULATION D1, D3: UPS120
C5 L1B* 100F 10V TANT
+
OUTPUT -5V
D3
1767 F11
Figure 11. Dual Output SEPIC Converter
8
76
5
0.0256 (0.65) BSC
0.005 0.002 (0.13 0.05)
1
23
4
MSOP (MS8) 1100
sn1767 1767fas
15
LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
PACKAGE DESCRIPTION
MS8E Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
0.889 0.127 (.035 .005) 3.00 0.102 (.118 .004) (NOTE 3) BOTTOM VIEW OF EXPOSED PAD OPTION 8 7 65 0.52 (.206) REF 1 2.06 0.102 (.080 .004) 1.83 0.102 (.072 .004)
2.794 0.102 (.110 .004)
5.23 (.206) MIN
2.083 0.102 3.2 - 3.45 (.082 .004) (.126 - .136)
0.42 0.04 (.0165 .0015) TYP
0.65 (.0256) BSC
GAUGE PLANE 0.53 0.015 (.021 .006) DETAIL "A" 0.18 (.077) 1 1.10 (.043) MAX 23 4 0.86 (.034) REF 8
RECOMMENDED SOLDER PAD LAYOUT
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
RELATED PARTS
PART NUMBER LT1370 LT1371 LT1372/LT1377 LT1374 LT1375/LT1376 LT1507 LT1576 LT1578 LT1616 LT1676/LT1776 LTC1765 LTC1877 LTC1878 LTC3401 LTC3402 LTC3404 DESCRIPTION High Efficiency DC/DC Converter High Efficiency DC/DC Converter 500kHz and 1MHz High Efficiency 1.5A Switching Regulators High Efficiency Step-Down Switching Regulator 1.5A Step-Down Switching Regulators 1.5A Step-Down Switching Regulator 1.5A Step-Down Switching Regulator 1.5A Step-Down Switching Regulator 600mA Step-Down Switching Regulator Wide Input Range Step-Down Switching Regulators 1.25MHz, 3A Wide Input Range Step-Down DC/DC High Efficiency Monolithic Step-Down Regulator High Efficiency Monolithic Step-Down Regulator Single Cell, High Current (1A), Micropower, Synchronous 3MHz Step-Up DC/DC Converter Single Cell, High Current (2A), Micropower, Synchronous 3MHz Step-Up DC/DC Converter 1.4MHz High Efficiency, Monolithic Synchronous Step-Down Regulator COMMENTS 42V, 6A, 500kHz Switch 35V, 3A, 500kHz Switch Boost Topology 25V, 4.5A, 500kHz Switch 500kHz, Synchronizable in SO-8 Package 500kHz, 4V to 16V Input, SO-8 Package 200kHz, Reduced EMI Generation 200kHz, Reduced EMI Generation 1.4MHz, 4V to 25V Input, SOT-23 Package 60V Input, 700mA Internal Switches VTH = 3V to 25V, SO-8 and TSSOP-16E Packages 550kHz, MS8, VIN Up to 10V, IQ =10A, IOUT to 600mA at VIN = 5V 550kHz, MS8, VIN Up to 6V, IQ = 10A, IOUT to 600mA at VIN = 3.3V VIN = 0.5V to 5V, Up to 97% Efficiency Synchronizable Oscillator from 100kHz to 3MHz VIN = 0.7V to 5V, Up to 95% Efficiency Synchronizable Oscillator from 100kHz to 3MHz Up to 95% Efficiency, 100% Duty Cycle, IQ = 10A, VIN = 2.65V to 6V
Burst Mode is a trademark of Linear Technology Corporation.
sn1767 1767fas
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.88 0.1 (.192 .004)
3.00 0.102 (.118 .004) NOTE 4
SEATING PLANE
0.22 - 0.38 (.009 - .015)
0.65 (.0256) BCS
0.13 0.05 (.005 .002)
MSOP (MS8E) 0102
LT/TP 0302 REV A 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 1999

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